Digital controlled oscillators (DCO) are important components of electronic devices, such as communication devices, synthesizers, and the like. DCOs generate a digitally variable clock signal at a frequency specified by digital information, such as a control word or control bits. The control word provided to the DCOs can be modified to change or alter the frequency of the output clock signal.
In communication circuits, phase locked loops (PLLs) are important components. PLLs enable synchronization between the receiver's carrier signal and the transmitted carrier signal by regulating the phase and frequency of carrier signals used within a device according to a reference signal. PLLs often utilize DCOs to generate the digital variable clock signal in an RF frequency band, which may then be provided to one or more dividers and a feedback path.
The PLL can adjust the variable clock signal to synchronize the receiver carrier signal and the transmitted carrier signal by adjusting the frequency of the variable digital clock. This PLL feedback loop synchronizes the variable clock signal CLKV with a reference clock REF (i.e., causing the frequency of the variable clock signal CLKV to ‘track’ the reference signal REF). The PLL adjusts the frequency of the digital variable clock signal by altering the control word provided to the DCO.
Typically, the frequency of the DCO is adjusted by altering a capacitance value input to the DCO. Varactors, also referred to as variable capacitors, are devices whose capacitance varies as a function of a voltage applied on its terminals. Varactors include varactor diodes and varactor devices implemented in CMOS. In general DCOs are comprising an array of varactors for frequency tuning. The varactors are turned on or off according to the control word thereby altering the capacitance to the DCO and the frequency.
An example of a prior art varactor configuration is shown in FIGS. 1A and 1B. FIG. 1A depicts a portion of a prior art varactor configuration. The configuration shows a single slice 110 of the varactor configuration. The slice includes four (4) unit cells 101, 102, 103 and 104. Each unit cell includes two (2) unit varactors, 101a, 101b, 102a, 102b, 103a, 103b, 104a, and 104b. Thus, unit cell 101 includes varactors 101a and 101b. Control lines are needed for each varactor. Thus, the slice shown in FIG. 1A requires control lines for the eight (8) varactors shown.
FIG. 1B depicts the slices 120 of the prior art varactor configuration. In this example, there are 64 slices, each slice having 4 unit cells, each unit cell having two varactors for a total of 512 addressable varactors. The slices can be arranged in top and bottom banks wherein the top bank includes slices #32-#63 and the bottom bank includes slices #0-#31. The varactors are addressable in a meander like scheme.
FIG. 1B shows the meander like addressing scheme in that varactors in slices #0, #1, and #2 have been turned on and varactors in slice #3 are in the process of being turned on (logical 1). The remaining slices #4-#63 are turned off (0).
Each varactor is individually addressable, thus 8 control lines for each slice are required. As a result, there are 512 control lines needed to individually address all of the varactors in this configuration. This results in a complex, power consuming logic circuit.